1. Field of the Invention
The present invention relates to a semiconductor device provided with a sense amplifier amplifying a signal voltage read out from a memory cell to a bit line, and particularly relates to a semiconductor device employing hierarchical bit lines and hierarchical sense amplifiers.
2. Description of Related Art
A semiconductor memory device such as DRAM is provided with sense amplifies each amplifying a signal voltage read out from a memory cell through a bit line. With a recent increase in capacity of the semiconductor memory device, a configuration has been proposed as measures against an increase in the number of memory cells connected to the bit line, in which a bit line structure and a sense amplifier structure are hierarchical respectively (For example, refer to Patent References 1 and 2). A memory cell array having the hierarchical structure can employ single-ended sense amplifiers having a small circuit scale without using a differential type sense amplifier circuit. Data corresponding to “0” or “1” stored in a memory cell of the DRAM is read out to the single-ended sense amplifier and is converted into a drain current of a transistor, and the signal voltage changing in response to the drain current is detected by a latch circuit included in a subsequent global sense amplifier which is configured to determine whether the data is “0” or “1”.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2002-56681    [Patent Reference 2] Japanese Patent Application Laid-open No. H5-266658
Generally, data stored in the memory cell of the DRAM is lost mainly due to that charge stored in a capacitor of the memory cell leaks through a junction. Particularly, “High” data is written into the memory cell when accessing or refreshing the memory cell, the stored charge in the capacitor is decreased with time. The leak of the stored charge in the memory cell of the DRAM generally has a temperature dependence and tends to become larger at a high temperature than at a low temperature. Thereby, in the above configuration having the hierarchical sense amplifiers, current ability becomes lower at the high temperature than at the low temperature, which causes the signal voltage inputted to the latch circuit of the above global sense amplifier to change slowly. As a result, there arises a problem that latch timing of the latch circuit has come before the signal voltage sufficiently changes so as to cause false latching. Further, this problem becomes significant particularly when reading “High” data at the high temperature, and thus read margin of the “High” data decreases at the high temperature. Therefore, there arise a problem that read margins of “High” data and “Low” data cannot be kept balanced. Conventionally, the configuration of the single-ended sense amplifier has been widely known (for example, see Patent Reference 1), and a circuit configuration for detecting the temperature in the DRAM has been known (for example, see Patent Reference 2). However, a configuration capable of dealing with the above-mentioned problems caused by the temperature dependence of the leak in the memory cell has not been known yet.